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2021

Muti-Pipeline Design of Systolic Array

Muti-Pipeline Design of Systolic Array

Pipelined-TPU

2020

A Parallel Optimization Design for Demosaicing

A Parallel Optimization Design for Demosaicing

Parallel-Demosaicing

Redesigned Eyeriss with Pipeline Implementation

Redesigned Eyeriss with Pipeline Implementation

Pipelined-Eyeriss

Projects

  • Parallel-Demosaicing1
  • Pipelined-Eyeriss1
  • Pipelined-TPU1

Tags

Accelerator2
fpga1
riscv1
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