A Parallel Optimization Design for Demosaicing
Summary
Verilog，Modelsim, Quarus II, FPGA
- 使⽤ FPGA 实现去⻢赛克&中值滤波的硬件结构，使⽤ wujian100 作为控制模块
- 增加并⾏去⻢赛克模块节约了 40%的 Liner-Buffer（相较传统架构）
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Verilog，Modelsim, Quarus II, FPGA